Performance-aware test-time optimization schemes for analysis of logic level faults in channels of on-chip networks

Show simple item record Bhowmik, Biswajit 2019-07-17T05:37:19Z 2019-07-17T05:37:19Z 2018
dc.identifier.other ROLL NO.11610103
dc.description Supervisors: Santosh Biswas and Jatindra Kumar Deka en_US
dc.description.abstract Today manycore, multiprocessor systems-on-chip (MPSoCs) have been introduced to cope with the growing demand for high-speed communication requirements of intensive-computing applica- tions. However, in spite of rapid advancements in deep-submicron (DSM) technology and the seam- less integration of intellectual property (IP) modules in the SoCs, these bus-based interconnection architectures have become unable to meet the performance requirements { bandwidth, throughput, latency, power, etc. in the applications where high-performance computation and communication is the dominant consideration. In other words, such SoCs often fail to sustain high-volume com- putation and high-speed communication among their components due to the use of global buses as the interconnects. The network-on-chip (NoC) as an alternate prevalent interconnection infras- tructure has been continuously occupying the space of the SoC. An NoC comprises a large number of IP cores, routers, and high-speed channels (interconnects) that construct a structure (topology) spanning across the chip. However, aggressive CMOS scaling expedites interconnect and transistor wear-out, shortening the lifespan of these basic components which are often vulnerable to a number of manufacturing and transient faults due to aging, physical defects, or hostile attacks invoked by malicious third parties. For instance, basic classical logic level faults treated as the manufactur- ing faults, such as stuck-at, open, and shorts in NoC channels cause various system-level failures and subsequent degradation of reliability, yield, and performance of the computing platform. One approach to tackle channel-faults in NoCs is to replace the faulty channel-wires with spare wires. Such scheme is not cost-e ective as the area overhead is substantially increased. Another approach is to exercise a fault-tolerant routing algorithm that directs tra c (application data packets) over channels by avoiding the faulty wires or an alternative fault-free path in order to connect the source and destination nodes, keeping the NoC functional. en_US
dc.language.iso en en_US
dc.relation.ispartofseries TH-1983;
dc.title Performance-aware test-time optimization schemes for analysis of logic level faults in channels of on-chip networks en_US
dc.type Thesis en_US

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